A system on chip (SOC) integrates multiple functions on an integrated circuit of a device, thereby providing higher performance, lower memory requirements, higher system reliability, and lower consumer costs. However, one key design constraint for an SOC is its tendency to dissipate large amounts of power. Specifically, input/output (I/O) power leakage from a device, including an SOC, is a form of power dissipation that affects the battery life of the device during standby modes.
In some cases, the SOC may include a Universal Serial Bus (USB) subsystem. The USB subsystem may also include a physical layer (PHY) that requires a high voltage rail (e.g., 3.3 V) and a continuous power-ON status, even in a stand-by mode, in order to detect any USB port state change events, e.g., the attachment or detachment of a USB cable. This combination of a high-pad voltage and a continuous power-ON requirement on the USB PHY subsystem lends to one of the highest I/O power leakage contributors on the SOC.
The same numbers are used throughout the disclosure and the figures to reference like components and features. Numbers in the 100 series refer to features originally found in FIG. 1; numbers in the 200 series refer to features originally found in FIG. 2; and so on.